1. Field of the Invention
The present invention relates to a phase aligner, and more particularly, to a phase aligner that receives incoming data and outputs retimed data in accordance with a recovered clock signal.
2. Description of the Related Art
High speed digital logic systems frequently run in a coherent manner, that is, a clock signal is distributed throughout the system to control the timing of system operation. When such systems run at high speeds, timing skew can occur between the clock signal and the data. Timing skew is a misalignment of the clock and data phases from the desired alignment. For example, data transitions are usually said to occur during the portion of the clock cycle displaced from the clock transitions by a predetermined amount .DELTA..phi. (delta phi). This is to allow data switching to complete before a clock transition occurs so that there is no ambiguity in detection of the data transition and so that undesirable metastable logic states do not occur. When timing (clock) is present, the .DELTA..phi. becomes larger or smaller than desired. If this differing .DELTA..phi. is left uncorrected, serious data transmission and data processing errors may occur.
Further, in other systems, when the data is transmitted to another portion of a circuit board or across wires to another part of the digital logic system, the clock is typically not transmitted because it produces a substantial amount of high frequency noise. Instead, the portion of the digital logic system receiving the incoming data first recovers the clock from the incoming data and then retimes the data so that the phases are displaced by the appropriate amount .DELTA..phi..
Timing skew is particularly severe where data and clocks are transmitted to different parts of a digital logic system over different distances and where the various parts of the system are at different temperatures. Under these circumstances, the data and the local clock phases may be misaligned and/or vary with time or temperature. It is not uncommon for the variation in phases between the data and the local clock to change dynamically. The local clock is the clock signal present on the part of the system of interest and may be a distributed form of the system clock or a locally generated or regenerated clock or a clock produced in some other way that is coherent with the system clock. Dynamic phase skews are also referred to as phase jitter.
Timing adjustments are used to compensate for the timing or phase skew. One way to correct the skew is to measure the phase difference between the data and the local clock and then provide timing adjustments. In the past, these timing adjustments have been provided by different lengths of coaxial cable which were used to equalize the propagation time. Such an arrangement of coaxial cable is not only ackward, but costly. This technique is difficult to use over a broad range of frequencies and is unable to compensate for dynamic skew, that is, phase errors that change with time, temperature, etc. Another approach to provide timing adjustments is to use a quartet sampler or other circuitry which produces quadrature clocks. However, producing the quadrature clocks is difficult, and becomes more difficult as the operating frequency increases.
FIG. 1 is a generalized block diagram of a conventional phase aligning system 100. The phase aligning system 100 includes a phase aligner 102 which receives incoming data 106 and a local clock 104. The phase aligner 102 operates to produce retimed data 108 and it associated clock 110 using the incoming data 106 and a local clock 104.
There are a variety of known schemes that have been used to perform the operations associated with the phase aligner 102 shown in FIG. 1. Examples of these known phase alignment schemes are described in U.S. Pat. Nos. 5,278,873; 5,081,655; 4,821,297; 4,773,085; 4,756,011; 4,821,296; 4,841,551; 4,839,907; 4,623,805 and 4,637,018.
FIG. 2 is a block diagram of a conventional phase aligner 102. The phase aligner 102 uses quadrature clocks which are offset from a local clock 104 by a certain phase difference. A phase detector 200 receives a feedback signal and the local clock 104. Based on the difference between the phase of these two signals, the phase detector 200 produces an output signal which is filtered by low-pass filter 201 to control a voltage-controlled oscillator (VCO) 202. The VCO 202 produces four quadrature clock signals .phi.1, .phi.2, .phi.3 and .phi.4, as well as the feedback signal. The quadrature clock signals are typically .phi.(0), .phi.(90), .phi.(180), and .phi.(270), where the number contained within the parentheses refers to the phase of the clock signal. The frequencies of the quadrature clocks are all the same frequencies as the local clock 104. The quadrature clock signals are supplied to a sample & encode unit 204 and a multiplexer (MUX) 206. The sample & encode unit 204 receives the incoming data, and based on the transitions of the incoming data, determines which of the four quadrature clocks most closely aligns with the phase of the incoming data. More specifically, the sample & encode unit 204 samples the incoming data using the four quadrature clocks and then encodes the sampled signals to determine which of the four quadrature clocks has the most desirable phase such that the incoming data would be closely aligned with the particular quadrature clock. The sample & encode unit 204 produces an output signal which is sent to a select input of the MUX 206. The MUX 206 then selects the one of the quadrature clocks that the sample & encode unit 204 has determined is most appropriate. The clock output from the MUX 206 is then used to clock the incoming data 106 into the flip-flop 208. The output of the flip-flop 208 is the retimed data 108.
The phase aligner 102 as shown in FIG. 2 is troublesome to manufacture because the incoming data and the quadrature clocks are asynchronous and metastable states are very likely to occur in the sample & encode unit 204, especially during high frequency operation. Metastable states are ambiguities caused by sampling the signal at its transition point which cause the digital data to get stuck between logic states. When metastable states occur, other digital logic will often see a glitch caused by the metastable state going from its metastable condition to its stable logic state. The metastability problem worsens as the operating frequency increases because less time is available for the sample & encode unit 204 to produce a stable output. Consequently, manufacturing the phase aligner 102 requires a lot of manufacturing data to confirm that metastable states will not cause a loss of data.
Due to differences in the geometric layout of the data signal and the clock signal traces at the printed circuit board or back plane level and due to the fact that the data may have different sources, there is an unknown phase offset between the clock and the data. This phase offset, although generally relatively fixed, may be time varying for numerous reasons (e.g., temperature). As the digital networks (i.e., telecommunications networks) evolve to support higher speeds and synchronous architectures, the greater the difficulties of effectively and economically bringing numerous digital channels (asynchronous data with known average frequency but unknown phase) into phase alignment for subsequent synchronous processing. The resulting advantages of phase alignment are that clocks need not be routed with data, precise matching of transmission line lengths is not required, and switches and multiplexers operate more reliably from a single master clock. Hence, the availability of an inexpensive means of phase alignment can simplify the architecture of new systems and can substantially reduce cost.
Thus, there is a need for a phase aligner which can be reliably manufactured without the difficulties associated with metastable states.